Notes for Computer Architecture A Quantitative Approach Sixth Edition

Navigating

1. Basic concepts : Chapter 1, Appendix A.
2. Memory Hierarchy: Appendix B, Chapter 2, and Appendices D and M.
3. Instruction-Level Parallelism: Appendix C, Chapter 3, and Appendix H.
4. Data-Level Parallelism: Chapters 4, 6, and 7, Appendix G.
5. Thread-Level Parallelism: Chapter 5, Appendices F and I.
6. Request-Level Parallelism: Chapter 6.
7. ISA: Appendices A and K.
8. Appendix E.

Appendix E can be read at any time, but it might work better if read after the ISA and cache sequences. Appendix J can be read whenever arithmetic moves you. You should read the corresponding portion of Appendix M after you complete each chapter.

Part I: Basic Concepts

1.1 Chapter 1 Fundamentals of Quantitative Design and Analysis

Amdahl’s Law prescribes practical limits to the number of useful cores per chip.

Classes of Computers

• IoTs/Embeded Computers
• Personal mobile device (PMD)
• Desktop
• Server
• Clusters/Warehouse scale computers (WSC)

Classes of parallelism and parallel architectures

• Data-Level Parallelism (DLP)
• Instruction-Level Parallelism (ILP)
• Thread-Level Parallelism (TLP)
• Request-Level Parallelism (RLP)

RISC-V registers, names, usage, and calling conventions.

The base RISC-V instruction set architecture formats.

Bandwidth grows by at least the square of the improvement in latency.

The energy consumption required per transistor:

$$Energy_{dynamic}\propto1/2\times {Capacitive load} \times {Voltage}^2$$

The power rqquied per transistor:

$${Power}_{dynamic}\propto 1/2\times{Capacitive load} \times {Voltage}^{2} \times {Frequency switched}$$

Modern microprocessors offer many techs to try to improve energy efficiency:

• Do nothing well.
• Dynamic voltage-frequency scaling (DVFS).
• Design for the typical case.
• Overclocking

Static power of a CMOS:

$${Power}_{static} \propto {Current}_{static}\times{Voltage}$$

The only hope to stop leakage is to turn off power to the chips’ subsets.

Comparson of the energy and die area of arithmetic operations and energy cost of accesses to SRAM and DRAM.

Cost of an integrated circuit:

$$\text{Cost of integrated circuit} = \frac{\text{Cost of die} + \text{Cost of testing die} + \text{Cost of packaging and final test}}{\text{Final test yield}}$$ $$\text{Cost of die} = \frac{\text{Cost of wafer}}{\text{Dies per wafer}\times \text{Die yield}}$$ $$\text{Dies per wafer} = \frac{\pi \times ({\text{Wafer diameter}/2})^2}{\text{Die area}} - \frac{\pi \times \text{Wafer diameter}}{\sqrt{2\times \text{Die area}}}$$

Bose-Einstein formula (Calcuting the die yield):

$$\text{Die yield} = \text{Wafer yield}\times1/(1+\text{Defects per unit area}\times\text{Die area})^N$$

There are two main measures for dependability

• Module reliability: mean time to failure (MTTF), falures in time (FIT), mean time to repair (MTTR).
• Module availabillity $$\text{Module availability} = \frac{MTTF}{MTTF + MTTR}$$

Computing SPECRation arithmetically:

$$\text{Geometric mean} = \sqrt[n]{\prod^n_{i = 1}sample_i}$$

CPU time for a program:

$$\text{CPU time} = \text{CPU clock cycles for a program}\times\text{Clock cycle time} = \frac{\text{CPU clock cycles for a program}}{\text{Clock rate}}$$

1.2 Appendix A Instruction Set Principles

Classifying ISA:Stack, Accumulator, Register-memory, and Register-register/load-store.

Little Endian

Big Endian

Memory addressing mode: displacement, immediate, and register indirect.

Reference

• [1] Computer Architecture A Quantitative Approach Sixth Edition